Demonstrating real-time and low-latency quantum error correction with superconducting qubits
Systems R&D
Quantum error correction will be essential for quantum computers to realize their full potential. As quantum computers advance towards demonstrating a universal fault-tolerant logical gate set, implementing scalable and low-latency real-time decoding will be crucial to avoid an exponential slowdown and maintain a fast logical clock rate. Here, we demonstrate low-latency feedback with a scalable FPGA decoder integrated into the control system of a superconducting quantum processor.
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