Quantum. Quick. | Our 9-qubit QPU is ready to ship today
This is where you find technology as pioneering as your own work. The quantum hardware at the core of our systems is cooled by a dilution refrigerator. Take a look inside and click on the numbered points to see how it all comes together.
When the computer is operational, five casings (like the white one shown at the top of the image) envelop the machine. These cans nest inside each other and act as thermal and radiation shields, keeping everything super cold and vacuum-sealed.
These cables deliver and condition microwave signals to and from the chip to drive qubit operations and return the measured results.
These gold-plated copper plates separate cooling zones. At the bottom, they plunge to one-hundredth of a Kelvin—hundreds of times as cold as outer space.
At the lowest, coldest plate sits the most critical hardware, including amplifiers, additional cables, filters, and the mounts that hold the quantum processing unit.
The QPU (quantum processing unit) is a superconducting quantum integrated circuit that powers the quantum computer, inside a metal package that thermalizes it and shields it from the environment.
The Novera QPU, our 9-qubit QPU, gives you unprecedented access to quantum technology and empowers you to take your research to the next level. Best of all, it’s ready to ship today.
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Classical symmetric encryption algorithms use N bits of a shared secret key to transmit N bits of a message over a one-way channel in an information theoretically secure manner. This paper proposes a hybrid quantum-classical symmetric cryptosystem that uses a quantum computer to generate the secret key.
Learn MoreWe develop a hardware-efficient ansatz for variational optimization, derived from existing ansatze in the literature, that parametrizes subsets of all interactions in the Cost Hamiltonian in each layer. We treat gate orderings as a variational parameter and observe that doing so can provide significant performance boosts in experiments. We carried out experimental runs of a compilation-optimized implementation of fully-connected Sherrington-Kirkpatrick Hamiltonians on a 50-qubit linear-chain subsystem of Rigetti Aspen-M-3 transmon processor.
Learn MoreHere, we demonstrate low-latency feedback with a scalable FPGA decoder integrated into the control system of a superconducting quantum processor. We perform an 8-qubit stability experiment with up to 25 decoding rounds and a mean decoding time per round below 1 \unit\micro, showing that we avoid the backlog problem even on superconducting hardware with the strictest speed requirements.
Learn MoreQuantum approximate optimization is one of the promising candidates for useful quantum computation, particularly in the context of finding approximate solutions to Quadratic Unconstrained Binary Optimization (QUBO) problems. However, the existing QPUs are relatively small, and canonical mappings of QUBO via the Ising model require one qubit per variable, rendering direct large-scale optimization infeasible. In classical optimization, a general strategy for addressing many large-scale problems is via multilevel/multigrid methods, where the large target problem is iteratively coarsened, and the global solution is constructed from multiple small-scale optimization runs. In this work, we experimentally test how existing QPUs perform as a sub-solver within such a multilevel strategy.
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