Demonstrating real-time and low-latency quantum error correction with superconducting qubits
Systems R&D
Here, we demonstrate low-latency feedback with a scalable FPGA decoder integrated into the control system of a superconducting quantum processor. We perform an 8-qubit stability experiment with up to 25 decoding rounds and a mean decoding time per round below 1 \unit\micro, showing that we avoid the backlog problem even on superconducting hardware with the strictest speed requirements.
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